1. Field of the Invention
The present invention relates to semiconductor technology, and more particularly, to a method of manufacturing semiconductor device and a wafer.
2. Description of the Related Art
In modern semiconductor processes, the shape and implantation energy of a polysilicon gate have strong impact on gate oxide reliability.
FIG. 8 is a graph showing the variation in NMOST (N-channel Metal-Oxide-Semiconductor Field-effect transistor) gate source/drain overlap capacitance as a function of the shape of a polysilicon gate (see Yung-Huei Lee, et al, IEDM 04-481 19.3.1). In FIG. 8, curve a, b and c respectively indicate the variations in gate source/drain overlap capacitance of a gate with reentrants on the bottom, a gate with a straight wall on the bottom and a gate with foot on the bottom.
FIG. 9A-9B is a graph showing comparison of the NMOST
TDDBs (Time-Dependent Dielectric Breakdown) as a function of the shape of a polysilicon gate. The curve a, b and c respectively indicate the shapes of the polysilicon gates which are respectively with reentrants on the bottom, a straight wall on the bottom and foot on the bottom (see Yung-Huei Lee, et al, IEDM 04-481 19.3.1). FIG. 9A is a graph showing the variation in NMOST TDDB of area structure (30×15 μm2) as a function of the shape of a polysilicon gate. FIG. 9B is a graph showing the variation in NMOST TDDB of edge structure (2000 μm×60 nm) as a function of the shape of a polysilicon gate. Stresses are performed at different e-fields for the two structures. There is no significant difference in TDDB distribution of area structure between the three splits. However, for the edge structure, the mean time of failure (MTF) of the polysilicon gate with foot on the gate bottom shows about 2.5× reduction than the other two splits.
It can be observed by the above figures that the polysilicon gate with foot tends to cause more gate-to-LDD overlap, and brings larger device overlap capacitance; the polysilicon gate with foot allows high energy implant to penetrate through the edge of the gate oxide which may downgrade the reliability of the gate oxide, and cause polysilicon gate edge TDDB failure. In prior art, there is no process or method for controlling the producing of polysilicon gates with reentrants well.